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---- INSTRUCTION DECODE ---> EXECUTE
------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ID_EX_REG is
	
	PORT (
	
	-- CONTROL signals
	REG_DEST_SELECTOR_IN : in STD_LOGIC; -- From bits 25 downto 21 or 20 downto 16
	ALU_BRANCH_IN : in STD_LOGIC; -- Is this a branch statement?
	MEM_TO_REG : in STD_LOGIC; -- Is this a load word instruction?
	
	-- DATA signals
	REG_DEST_1_IN : in STD_LOGIC_VECTOR(4 downto 0);
	REG_DEST_2_IN : in STD_LOGIC_VECTOR(4 downto 0);
	IMMEDIATE_VAL_IN : in STD_LOGIC_VECTOR(31 downto 0);
	PC_IN : in STD_LOGIC_VECTOR(31 downto 0);
	ALU_OP1_IN : in STD_LOGIC_VECTOR(31 downto 0);
	ALU_OP2_IN : in STD_LOGIC_VECTOR(31 downto 0);
	
	
	-- OUTPUT signals
	REG_DEST_OUT : 
	
	);

end ID_EX_REG;

architecture Behavioral of ID_EX_REG is

begin


end Behavioral;

